GPU Design Verification Intern

In this highly visible role, the Unit Level Design Verification Engineer will be responsible for the pre-silicon verification of embedded graphics cores.  

Core responsibilities include:

• Support the design through RTL development and into production
  
• Develop verification plans, create verification test bench components, generate tests, run simulations, and debug design issues
  
• Create functional coverage points, analyze coverage, and enhance test environment to target coverage holes
  
• Provide in-depth knowledge of architecture, implementation, verification, and debug  
  
• Utilize skills including UNIX and Perl to create efficient, automated verification flows
  
• Apply knowledge of hardware description languages (VHDL/Verilog), hardware verification languages (SystemVerilog/UVM/OVM), and logic simulators to verify complex designs
  

Qualifications:

• Verification language such as SystemVerilog/UVM/OVM, Verilog/VHDL; Specman experience is a plus
  
• Expertise with various HDL simulators and waveform viewers like NCSIM, ModelSim, VCS, DVE, Verdi
  
• Perl, Shell scripting, Makefiles, TCL
  
• Good knowledge of Computer Architecture, General Purpose Microprocessor and Memory sub-system micro-architecture
  
• Experience defining coverage space, writing coverage model, analyzing results
  
• Graphics architecture and programming (OpenGL/OpenCL) is a plus
  

Education:

• BSEE/MSEE 3+ years of experience preferred